Cryptovia | Cryptographic libraries for AVR CPU
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Cryptographic libraries for AVR CPU

AES Algorithms for AVR CPU

FIPS 197 compliant

 

Three different AES implementations in AVR assembly language are available:

  1. One has been designed for speed for products requiring high throughput.
  2. Another one has been optimized with small code footprint objective for products where any byte memory counts.
  3. The last one is a trade-off between speed and memory size.

 

The table below shows the memory occupation and the timings of the three implementations for each AES key length on a AVR core.

 

Algorithm Version ROM RAM Cycles per 16-byte block
encryption / decryption
Throughput Kbit/s @16MHz
encryption / decryption
AES-128 Speed 2 424 52 3 893 / 6 015 513 / 332
Code 1 216 57 8 013 / 10 539 249 / 190
Tradeoff 1 700 56 5 474 / 7 487 365 / 267
AES-192 Speed 2 800 82 5 550 / 8 579 360 / 233
Code 1 320 86 11 296 / 15 392 177 / 130
Tradeoff 1 638 86 8 183 / 12 325 244 / 162
AES-256 Speed 2 742 68 5 552 / 8 558 360 / 237
Code 1 310 72 11 718 / 15 293 170 / 130
Tradeoff 2 066 72 7 662 / 10 609 261 / 188

 

Contact us for an evaluation version of the AES library.

DES Algorithms for AVR CPU

FIPS 46 compliant

 

One DES/TDES implementation in AVR assembly language is available.

 

The table below shows the memory occupation and the timings of the implementation for each DES key length on a AVR core.

 

Algorithm ROM RAM Cycles per 8-byte block
encryption / decryption
Throughput Kbit/s @16 MHz
encryption / decryption
DES 1 748 52 10 518 / 10 493 95 / 95
TDES-2K 1 748 60 31 567 / 31 542 32 / 32
TDES-3K 1 748 60 31 567 / 31 546 32 / 32

 

Contact us for an evaluation version of the DES library.

Hash Functions for AVR CPU

FIPS 180, FIPS 198 and RFC 1321 compliant

 

One implementation in AVR assembly language of the hash functions MD5, SHA-1, SHA-256/224 and SHA-512/384 is available.
HMAC constructions based on those hash functions are also available.

 

The table below shows the memory occupation and the timings of the implementations on a AVR core.

 

Algorithm ROM RAM Cycles to process
50 bytes
Throughput
Kbit/s @16 MHz
MD5 1 378 128 15 700 398
HMAC-MD5 1 662 219 63 629 98
SHA-1 1 174 135 25 701 243
HMAC-SHA-1 1 458 220 103 233 60
SHA-256 / SHA-224 1 656 165 42 744 146
HMAC-SHA-256/224 2 224 276 171 253 36
SHA-512 / SHA-384 2 812 302 106 224 58
HMAC-SHA-512/384 3 380 505 425 811 14

 

Contact us for an evaluation version of the hash library.

Deterministic Random Number Bits Algorithms for AVR CPU

NIST SP 800-90A compliant

 

Implementations for pseudo random numbers generation are available. The generations are based on AES encryptions, or hash functions or HMAC computations as described in the NIST SP 800-90A standard.

 

The table below shows the memory occupation and the timings of the implementations on a AVR core.

 

Algorithm ROM RAM Cycles to generate
128 bytes
Throughput
Kbit/s @16 MHz
DRBG AES-128 2 816 164 105 430 152
DRBG AES-192 3 038 224 168 837 95
DRBG AES-256 3 032 216 176 053 91
DRBG SHA-1 3 558 507 471 404 34
DRBG SHA-256 3 918 359 526 254 30,4
DRBG SHA-512 5 148 594 1 084 445 14,7
DRBG HMAC SHA-1 3 044 583 1 353 313 11,8
DRBG HMAC SHA-256 3 810 663 1 811 365 8,8
DRBG HMAC SHA-512 4 970 1 204 3 511 704 4,55

 

Contact us for an evaluation version of the hash library.

RSA Algorithms for AVR CPU

PKCS #1 compliant

 

 

One RSA implementation, with the core routines written in AVR assembly language, is available. The RSA computation using the CRT method is also supported.
In addition to plain RSA computations, the PSS signature scheme and the OAEP encryption padding method described in the PKCS #1 standard are also available.

The table below shows the memory occupation and the timings of the implementations on a AVR core.
The figures for RSA-OAEP and RSA-PSS are obtained with SHA-1 as the hash function for the mask generation function.

 

Algorithm Key Length ROM RAM Cycles Timing @16 MHz
RSA (e=2^16+1) 1 024 4 488 770 15 500 000 0,97 ms
CRT RSA 1 024 6 264 1 110 215 000 000 13,4 s
RSA-OAEP (e=2^16+1) 1 024 9 680 1 334 15 800 000 0,99 s
RSA-OAEP CRT 1 024 10 278 1 674 218 000 000 13,6 s
RSA-PSS (e=2^16+1) 1 024 12 934 1 486 15 800 000 0,99 s
RSA-PSS CRT 1 024 11 158 1 638 218 000 000 13,6 s

 

Contact us for an evaluation version of the RSA library.

ECDSA for AVR CPU

FIPS 186 compliant

 

One generic ECDSA implementation over prime fields, with the core routines written in AVR assembly language, is available. Both ECDSA signature generation and ECDSA signature verification are supported.

The implementation does not take advantage of specific characteristics of the elliptic curves, and hence can support any prime field elliptic curve of any size. Especially all the elliptic curves over prime fields defined in the FIPS 186 standard are supported.

The table below shows the memory occupation and the timings of the implementations on a AVR core.

 

Algorithm ROM RAM Cycles for signature
generation / verification
Timing @16 MHz
generation / verification
ECDSA-192 14 426 918 86 000 000 / 173 000 000 5,37 s / 10,8 s
ECDSA-224 1 020 133 000 000 / 271 000 000 8,3 s / 16,9 s
ECDSA-256 1 122 195 000 000 / 398 000 000 12,2 s / 24,8 s

 

Contact us for an evaluation version of the ECDSA library.