Cryptovia | Cryptographic libraries for ARM Thumb CPU
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Cryptographic libraries for ARM Thumb CPU

AES Algorithms for ARM Thumb CPU

FIPS 197 compliant

 

Two different AES implementations in ARM Thumb assembly language are available:

  1. One has been designed for speed for products requiring high throughput.
  2. Another one has been optimized with small code footprint objective for products where any byte memory counts.

 

The table below shows the memory occupation and the timings of the two implementations for each AES key length on a ARM Cortex-M0 core.

 

Algorithm Version ROM RAM Cycles per 16-byte
encryption/decryption
Throughput Mbit/s @50 MHz
encryption/decryption
AES-128 Speed 3 998 56 2 270 / 4 328 2,69 / 1,41
Code 1 250 56 5 291 / 7 866 1,15 / 0,78
AES-192 Speed 4 204 92 2 633 / 4 831 2,32 / 1,26
Code 1 456 92 6 253 / 9 164 0,98 / 0,67
AES-256 Speed 4 240 72 3 104 / 5 780 1,97 / 1,06
Code 1 412 88 7 337 / 10 849 0,83 / 0,56

 

Contact us for an evaluation version of the AES library.

DES Algorithms for ARM Thumb CPU

FIPS 46 compliant

 

One DES/TDES implementation in ARM Thumb assembly language is available.

 

The table below shows the memory occupation and the timings of the implementation on a ARM Cortex-M0 core.

 

Algorithm ROM RAM Cycles per 8-byte block
encryption / decryption
Throughput Kbit/s @50 MHz
encryption / decryption
DES 1 300 72 30 958 / 30 961 101 / 101
TDES-2K 1 300 104 92 900 / 92 909 34 / 34
TDES-3K 1 300 104 92 905 / 92 913 34 / 34

 

Contact us for an evaluation version of the DES library.

Hash Functions for ARM Thumb CPU

FIPS 180, FIPS 198 and RFC 1321 compliant

 

One implementation in ARM Thumb assembly language of the hash functions MD5, SHA-1, SHA-256/224 and SHA-512/384 is available.
HMAC constructions based on those hash functions are also available.

 

The table below shows the memory occupation and the timings of the implementations on a ARM Cortex-M0 core.

 

Algorithm ROM RAM Cycles to process
50 bytes
Throughput
Mbit/s @50 MHz
MD5 768 52 3 262 5,85
HMAC-MD5 962 92 15 732 1,21
SHA-1 612 64 6 449 2,97
HMAC-SHA-1 812 108 28 461 0,69
SHA-256 / SHA-224 980 84 9 929 1,92
HMAC-SHA-256/224 1 380 140 42 263 0,45
SHA-512 / SHA-384 1 680 136 25 861 0,74
HMAC-SHA-512/384 2 080 208 133 628 0,14

 

Contact us for an evaluation version of the hash library.

RSA Algorithms for ARM Thumb CPU

PKCS #1 compliant

 

 

One RSA implementation, with the core routines written in ARM Thumb assembly language, is available. The RSA computation using the CRT method is also supported.

 

In addition to plain RSA computations, the PSS signature scheme and the OAEP encryption padding method described in the PKCS #1 standard are available.

 

The table below shows the memory occupation and the timings of the implementations on a ARM Cortex-M0 core.
The figures for RSA-OAEP and RSA-PSS are obtained with SHA-1 as the hash function for the mask generation function.

 

Algorithm Key Length ROM RAM Cycles Timing @50 MHz
RSA (e=2^16+1) 1 024 2 320 1 068 6 300 000 126 ms
2 048 2 320 1 708 25 000 000 500 ms
CRT RSA 1 024 3 278 1 516 92 500 000 1,85 s
2 048 3 278 2 412 670 000 000 13,4 s
RSA-OAEP (e=2^16+1) 1 024 4 526 1 660 6 400 000 128 ms
2 048 4 526 2 556 25 000 000 500 ms
RSA-OAEP CRT 1 024 5 484 2 164 92 500 000 1,85 s
2 048 5 484 3 796 670 000 000 13,4 s
RSA-PSS (e=2^16+1) 1 024 5 226 1 796 6 400 000 126 ms
2 048 2 820 5 226 25 000 000 500 ms
RSA-PSS CRT 1 024 6 184 2 108 93 700 000 1,87 s
2 048 6 184 3 260 670 000 000 13,4 s

 

Contact us for an evaluation version of the RSA library.

ECDSA for ARM Thumb CPU

FIPS 186 compliant

 

One generic ECDSA implementation over prime fields, with the core routines written in ARM Thumb assembly language, is available.

Both ECDSA signature generation and ECDSA signature verification are supported.

 

The implementation does not take advantage of specific characteristics of the elliptic curves, and hence can support any prime field elliptic curve of any size. Especially all the elliptic curves over prime fields defined in the FIPS 186 standard are supported.

 

The table below shows the memory occupation and the timings of the implementation on a ARM Cortex-M0 core.

 

Algorithm ROM RAM Cycles for signature
generation / verification
Timing @50 MHz
generation / verification
ECDSA-192 7 236 1 188 44 000 000 / 88 000 000 880 ms / 1,76 s
ECDSA-224 7 236 1 272 66 000 000 / 133 000 000 1,32 s / 2,66 s
ECDSA-256 7 236 1 344 93 000 000 / 187 000 000 1,86 s / 3,74 s
ECDSA-384 7 236 1 668 285 000 000 / 575 000 000 5,7 s / 11,5 s
ECDSA-521 7 236 2 072 725 000 000 / 1 450 000 000 14,5 s / 29 s

 

Contact us for an evaluation version of the ECDSA library.