Cryptovia | Cryptographic libraries for 8051 CPU
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Cryptographic libraries for 8051 CPU

AES Algorithms for 8051 CPU

FIPS 197 compliant

 

Three different AES implementations in 8051 assembly language are available:

  1. One has been designed for speed for products requiring high throughput.
  2. Another one has been optimized with small code footprint objective for products where any byte memory counts.
  3. The last one is a trade-off between speed and memory size.

 

The table below shows the memory occupation and the timings of the three implementations for each AES key length on a 8051 core.

 

Algorithm Version ROM RAM Cycles per 16-byte block
encryption / decryption
Throughput Kbit/s @12MHz
encryption / decryption
AES-128 Speed 2 246 32 3 008 / 4 400 499 / 341
Code 962 32 6 421 / 10 393 233 / 144
Tradeoff 1 340 32 4 010 / 6 052 374 / 248
AES-192 Speed 2 236 64 5 866 / 9 488 255 / 158
Code 1 133 64 9 118 / 14 270 164 / 105
Tradeoff 1 285 64 7 750 / 12 414 193 / 120
AES-256 Speed 2 394 48 4 476 / 6 463 335 / 232
Code 1 021 48 9 177 / 13 941 163 / 108
Tradeoff 1 539 48 7 054 / 9 809 212 / 153

 

Contact us for an evaluation version of the AES library.

DES Algorithms for 8051 CPU

FIPS 46 compliant

 

One DES/TDES implementation in 8051 assembly language is available.

 

The table below shows the memory occupation and the timings of the implementation for each DES key length on a 8051 core.

 

Algorithm ROM RAM XRAM Cycles per 8-byte block
encryption / decryption
Throughput Kbit/s @12 MHz
encryption / decryption
DES 1 570 32 4 12 450 / 12 546 60 / 60
TDES-2K 1 570 32 4 37 500 / 37 596 20 / 20
TDES-3K 1 570 32 4 37 500 / 37 596 20 / 20

 

Contact us for an evaluation version of the DES library.

Hash Functions for 8051 CPU

FIPS 180, FIPS 198 and RFC 1321 compliant

 

One implementation in 8051 assembly language of the hash functions MD5, SHA-1, SHA-256/224 and SHA-512/384 is available.
HMAC constructions based on those hash functions are also available.

 

The table below shows the memory occupation and the timings of the implementations on a 8051 core.

 

Algorithm ROM RAM XRAM Cycles to process 50 bytes
(100 bytes for SHA-512/384)
Throughput
Kbit/s @12 MHz
MD5 1 265 20 85 17 152 273
HMAC-MD5 1 489 20 165 68 703 68
SHA-1 1 153 24 89 33 642 139
HMAC-SHA-1 1 377 24 178 135 633 34
SHA-256 / SHA-224 1 760 40 104 88 980 53
HMAC-SHA-256/224 2 208 40 200 357 345 13
SHA-512 / SHA-384 3 326 32 261 298 563 31
HMAC-SHA-512/384 3 774 32 453 1 196 621 7

 

Contact us for an evaluation version of the hash library.

RSA Algorithms for 8051 CPU

PKCS #1 compliant

 

One RSA implementation, with the core routines written in 8051 assembly language, is available. The RSA computation using the CRT method is also supported.

 

In addition to plain RSA computations, the PSS signature scheme and the OAEP encryption padding method described in the PKCS #1 standard are also available.

 

The table below shows the memory occupation and the timings of the implementations on a 8051 core.
The figures for RSA-OAEP and RSA-PSS are obtained with SHA-1 as the hash function for the mask generation function.

 

Algorithm Key Length ROM RAM XRAM Cycles Timing @12 MHz
RSA (e=2^16+1) 1 024 4 580 24 595 27 000 000 27 s
CRT RSA 1 024 7 021 24 932 376 000 000 376 s
RSA-OAEP (e=2^16+1) 1 024 9 696 24 1 353 27 000 000 27 s
RSA-OAEP CRT 1 024 12 344 24 1 717 379 000 000 379 s
RSA-PSS (e=2^16+1) 1 024 10 246 24 1 485 27 000 000 27 s
RSA-PSS CRT 1 024 13 204 24 1 655 380 000 000 380 s

 

Contact us for an evaluation version of the RSA library.

ECDSA for 8051 CPU

FIPS 186 compliant

 

One generic ECDSA implementation over prime fields, with the core routines written in 8051 assembly language, is available.
Both ECDSA signature generation and ECDSA signature verification are supported.

 

The implementation does not take advantage of specific characteristics of the elliptic curves, and hence can support any prime field elliptic curve of any size. Especially all the elliptic curves over prime fields defined in the FIPS 186 standard are supported.

 

The table below shows the memory occupation and the timings of the implementation on a 8051 core.

 

Algorithm ROM RAM XRAM Cycles for signature
generation / verification
Timing @12 MHz
generation / verification
ECDSA-192 15 869 19 1 242 151 000 000 / 304 000 000 151 s / 304 s
ECDSA-224 15 869 19 1 433 234 000 000 / 476 000 000 234 s / 476 s
ECDSA-256 15 869 19 1 589 342 000 000 / 699 000 000 342 s / 699 s

 

Contact us for an evaluation version of the ECDSA library.